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Advance Information June 2000
AS6UA51216
1.65V to 3.6V 512Kx16 IntelliwattTM low power CMOS SRAM with one chip enable Features
* * * * * * * * AS6UA51216 IntelliwattTM active power circuitry Industrial and commercial temperature ranges available Organization: 524,288 words x 16 bits 2.7V to 3.6V at 55 ns 2.3V to 2.7V at 70 ns 1.65V to 2.3V at 100 ns Low power consumption: ACTIVE - 144 mW at 3.6V and 55 ns - 68 mW at 2.7V and 70 ns - 28 mW at 2.3 V and 100 ns * Low power consumption: STANDBY - 72 W max at 3.6V - 41 W max at 2.7V - 28 W max at 2.3V * 1.2V data retention * Equal access and cycle times * Easy memory expansion with CS, OE inputs * Smallest footprint packages - 48-ball FBGA - 400-mil 44-pin TSOP II * ESD protection 2000 volts * Latch-up current 200 mA
Logic block diagram
A0 A1 A2 A3 A4 A6 A7 A8 A12 A13 I/O1-I/O8 I/O9-I/O16 WE Row Decoder VDD 512K x 16 Array (8,388,608) VSS
Pin arrangement (top view)
44-pin 400-mil TSOP II A4 1 A5 44 A3 2 43 A6 A2 3 42 A7 A1 4 41 OE 5 A0 UB 40 LB 6 39 CS I/O16 I/O1 7 38 I/O15 I/O2 8 37 I/O14 I/O3 9 36 I/O13 I/O4 10 35 VCC VSS 11 34 VSS VCC 12 33 I/O5 13 32 I/O12 I/O6 I/O11 14 31 I/O7 I/O10 15 30 I/O8 I/O9 16 29 WE A8 17 28 A18 18 A9 27 A17 A10 19 26 A16 20 25 A11 A15 21 A12 24 A14 22 A13 23
Note: A "MODE" pad is to be placed between pins 33 and 34 and 11 and 12, shorted. The bonding of this pad to VCC or VSS configures the device. There should only be 44+2+2 pads on the chip. Two extra VCC to separate out Array from Peripheral and Two-Mode Pads.
I/O buffer
Control circuit Column decoder A5 A9 A10 A11 A14 A15 A16 A17 A18
UB OE LB CS
48-CSP Ball-Grid-Array Package
A B C D E F G H
1 LB I/O9 I/O10 VSS VCC I/O15 I/O16 A18
2 3 OE A0 A3 UB I/O11 A5 I/O12 A17 I/O13 VSS I/O14 A14 NC A12 A8 A9
4 A1 A4 A6 A7 A16 A15 A13 A10
5 A2 CS I/O2 I/O4 I/O5 I/O6 WE A11
6 NC I/O1 I/O3 VCC VSS I/O7 I/O8 NC
Selection guide
VCC Range Product AS6UA51216 AS6UA51216 AS6UA51216 Min (V) 2.7 2.3 1.65 Typ2 (V) 3.0 2.5 2.0 Max (V) 3.6 2.7 2.3 Speed (ns) 55 70 100 Power Dissipation Operating (ICC1) Max (mA) 2 1 1 Standby (ISB2) Max (A) 20 15 12
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Copyright (c)2000 Alliance Semiconductor. All rights reserved.
AS6UA51216
Functional description
The AS6UA51216 is a low-power CMOS 8,388,608-bit Static Random Access Memory (SRAM) device organized as 524,288 words x 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 55/70/100 ns are ideal for low-power applications. Active high and low chip enables (CS) permit easy memory expansion with multiple-bank memory systems. When CS is high, or UB and LB are high, the device enters standby mode: the AS6UA51216 is guaranteed not to exceed 72 W power consumption at 3.6V and 55ns; 41 W at 2.7V and 70 ns; or 28 W at 2.3V and 100 ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption. A write cycle is accomplished by asserting write enable (WE) and chip enable (CS) low, and UB and/or LB low. Data on the input pins I/O1- O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE), chip enable (CS), UB and LB low, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, or (UB) and (LB), output drivers stay in high-impedance mode. These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O1-I/O8, and UB controls the higher bits, I/O9-I/O16. All chip inputs and outputs are CMOS-compatible, and operation is from either a single 1.65V to 3.6V supply. Device is available in the JEDEC standard 400-mL, TSOP II, and 48-ball FBGA packages.
Absolute maximum ratings
Parameter Voltage on V CC relative to VSS Voltage on any I/O pin relative to GND Power dissipation Storage temperature (plastic) Temperature with VCC applied DC output current (low) Device Symbol VtIN VtI/O PD Tstg Tbias IOUT Min -0.5 -0.5 - -65 -55 - 1.0 +150 +125 20 Max VCC + 0.5 Unit V V W
C C
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CS H L L L WE X X H H OE X X H L LB X H X L H L L L L X H L
Key: X = Don't care, L = Low, H = High.
UB X H X H L L H L L
Supply Current ISB ICC ICC
I/O1-I/O8 I/O9-I/O16 High Z High Z DOUT High Z DOUT DIN High Z High Z High Z DOUT DOUT High Z DIN DIN
Mode Standby (ISB) Output disable (ICC) Read (ICC)
ICC
High Z DIN
Write (ICC)
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Recommended operating condition (over the operating range)
Parameter VOH Description IOH = -2.1mA Output HIGH Voltage IOH = -0.5mA IOH = -0.1mA IOL = 2.1mA VOL Output LOW Voltage IOL = 0.5mA IOL = 0.1mA VIH Input HIGH Voltage Test Conditions VCC = 2.7V VCC = 2.3V VCC = 1.65V VCC = 2.7V VCC = 2.3V VCC = 1.65V VCC = 2.7V VCC = 2.3V VCC = 1.65V VCC = 2.7V VIL IIX IOZ ICC Input LOW Voltage Input Load Current Output Load Current VCC Operating Supply Current VCC = 2.3V VCC = 1.65V GND < VIN < VCC GND < VO < VCC; Outputs High Z CS = VIL, VIN = VIL or VIH, IOUT = 0mA, f=0 , CS < 0.2V VIN < 0.2V or VIN > VCC - 0.2V, f = 1 mS VCC = 3.6V VCC = 2.7V VCC = 2.3V VCC = 3.6V VCC = 2.7V VCC = 2.3V 2.2 2.0 1.4 -0.5 -0.3 -0.3 -1 -1 Min 2.4 2.0 1.5 0.4 0.4 0.2 VCC + 0.5 VCC + 0.3 VCC + 0.3 0.8 0.6 0.4 +1 +1 2 1 1 4 2 2 40/30/20 30/25/15 25/10/12 100 100 100 20 15 12 2
A A A A A
Max
Unit V
V
V
V
mA
ICC1 @ 1 MHz
Average VCC Operating Supply Current at 1 MHz
mA
ICC2
Average VCC Operating Supply Current
VCC = 3.6V (55/70/100 mS) CS VIL, VIN = VIL or VCC = 2.7V (55/70/100 mS) VIH, f = fMax VCC = 2.3V(55/70/100 mS) CS > VIH or UB = LB > VIH, other inputs = VIL or VIH, f = 0 VCC = 3.6V VCC = 2.7V VCC = 2.3V VCC = 3.6V VCC = 2.7V VCC = 2.3V VCC = 1.2V
mA
ISB
CS Power Down Current; TTL Inputs
ISB1
CS > VCC - 0.2V or CS Power Down Current; UB = LB > VCC - 0.2V CMOS Inputs other inputs = 0V - VCC, f = fMax Data Retention CS > VCC - 0.1V, UB = LB = VCC - 0.1V f=0
ISBDR
Capacitance (f = 1 MHz, T a = Room temperature, VCC = NOMINAL)
Parameter Input capacitance I/O capacitance Symbol CIN CI/O Signals A, CS, WE, OE, LB, UB I/O Test conditions VIN = 0V VIN = VOUT = 0V Max 5 7 Unit pF pF
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AS6UA51216
Read cycle (over the operating range)
-55 Parameter
Read cycle time Address access time Chip enable (CS) access time Output enable (OE) access time Output hold from address change CS o output in low Z
-70 Max - 55 55 25 - - 20 - 55 - 20 20 - 55 Min 70 - - - 10 10 0 5 - 10 0 0 0 - Max - 70 70 35 - - 20 - 70 - 20 20 - 70 Min 100 - - - 15 10 0 5 - 10 0 0 0 -
-100 Max - 100 100 50 - - 20 - 100 - 20 20 - 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 4, 5 4, 5 5 4, 5 4, 5 4, 5 3 3 Notes
Symbol tRC tAA tACS tOE tOH tCLZ tCHZ tOLZ tBA tBLZ tBHZ tOHZ tPU tPD
Min 55 - - - 10 10 0 5 - 10 0 0 0 -
CS high to output in high Z OE low to output in low Z UB/LB access time UB/LB low to low Z UB/LB high to high Z OE high to output in high Z Power up time Power down time
Shaded areas indicate preliminary information.
Key to switching waveforms
Rising input Falling input Undefined/don't care
Read waveform 1 (address controlled)
tRC Address tOH D OUT Previous data valid tAA Data valid tOH
Read waveform 2 (CS, OE, UB, LB controlled)
tRC Address tAA OE tOLZ CS tLZ LB, UB tBLZ DOUT tBA Data valid tBHZ tACS tOHZ tHZ tOE tOH
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Write cycle (over the operating range)
-55 Parameter
Write cycle time Chip enable to write end Address setup to write end Address setup time Write pulse width Address hold from end of write Data valid to write end Data hold time Write enable to output in high Z Output active from write end UB/LB low to end of write
-70 Max - - - - - - - - 20 - - Min 70 60 60 0 55 0 30 0 0 5 55 Max - - - - - - - - 20 - - Min 100 80 80 0 70 0 40 0 0 5 70
-100 Max - - - - - - - - 20 - - Unit ns ns ns ns ns ns ns ns ns ns ns 4, 5 4, 5 4, 5 12 12 Notes
Symbol tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW tBW
Min 55 40 40 0 35 0 25 0 0 5 35
Shaded areas indicate preliminary information.
Write waveform 1 (WE controlled)
tWC Address tCW CS tBW LB, UB tAS WE tDW D IN DOUT Data undefined tWZ Data valid tOW High Z tDH tAW tWP tAH
Write waveform 2 (CS controlled)
tWC Address tAS CS tCW tAW tBW LB, UB tWP WE tDW DIN DOUT tCLZ High Z tWZ Data undefined Data valid tOW High Z tDH tAH
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AS6UA51216
Data retention characteristics (over the operating range)
Parameter VCC for data retention Data retention current Chip deselect to data retention time Operation recovery time Symbol VDR ICCDR tCDR tR Test conditions VCC = 1.2V CS VCC - 0.1V or UB = LB = > VCC - 0.1V VIN VCC - 0.1V or VIN 0.1V Min 1.2V - 0 tRC Max 3.6 2 - - Unit V mA ns ns
Data retention waveform
Data retention mode VCC VCC tCDR CS VIH VDR VIH VDR 1.2V VCC tR
AC test loads and waveforms
VCC OUTPUT 30 pF R2 INCLUDING JIG AND SCOPE INCLUDING JIG AND SCOPE R1 VCC OUTPUT 5 pF R2 VCC Typ GND (b) Thevenin equivalent: R1 OUTPUT RTH V
ALL INPUT PULSES 90% 10% < 5 ns (c) 90% 10%
(a)
Parameters R1 R2 RTH VTH
Notes
1 2 3 4 5 6 7 8 9 10 11 12 13 14
VCC = 3.0V 1105 1550 645 1.75V
VCC = 2.5V 16670 15380 8000 1.2V
VCC = 2.0V 15294 11300 6500 0.85V
Unit Ohms Ohms Ohms Volts
During V CC power-up, a pull-up resistor to VCC on CS is required to meet ISB specification. This parameter is sampled, but not 100% tested. For test conditions, see AC Test Conditions. tCLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured 500 mV from steady-state voltage. This parameter is guaranteed, but not tested. WE is HIGH for read cycle. CS and OE are LOW for read cycle. Address valid prior to or coincident with CS transition LOW . All read cycle timings are referenced from the last valid address to the first transitioning address. CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. N/A. 1.2V data retention applies to commercial and industrial temperature range operations. C = 30pF, except at high Z and low Z parameters, where C = 5pF.
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Typical DC and AC characteristics
Normalized supply current vs. supply voltage 1.4 1.2 Normalized ICC 1.0 0.8 0.6 0.4 0.2 0.0 1.7 2.2 2.7 3.2 3.7 VIN = V CC typ TA = 25 C 1.0 Normalized access time vs. supply voltage 3.0 2.5 Normalized TAA Normalized ISB2 0.75 TA = 25 C 0.5 2.0 1.5 1.0 0.5 0.0 -0.5 0.0 1.7 2.2 2.7 3.2 3.7 -55 25 105 Ambient temperature (C) Normalized ICC vs. cycle time 1.5 VCC = 3.6V TA = 25 C VCC = VCC typ VIN = VCC typ Normalized standby current vs. ambient temperature
0.25
Supply voltage (V) Normalized standby current vs. supply voltage 1.4 1.2 Normalized ISB 1.0 0.8 0.6 0.4 0.2 0.0 1 2.8 1.9 Supply voltage (V) 3.7 VIN = VCC typ TA = 25 C ISB2
Supply Voltage (V)
Normalized ICC
1.0
0.50
0.10 1 5 10 Supply voltage (V) 15
Package diagrams and dimensions
44-pin TSOP II
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
c
Min (mm) A A1 A2 b c d e He E l 0.05 0.95 0.25 20.85 10.06 11.56 0.40
Max (mm) 1.2 1.05 0.45 21.05 10.26 11.96 0.60
44-pin TSOP II
e He
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
d l 0-5
0.15 (typical)
A A1 b E
A2
0.80 (typical)
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AS6UA51216
48-ball FBGA Bottom View 6 5 4 3 2 1 Ball #A1 Top View Ball #A1 Index
A B C D E F G H Elastomer A B1 B A C1 SRAM Die C
Side View
2
Detail View A
D E2 E Die
1
Y Die 0.3/Typ
Minimum A B B1 C C1 D E E1 E2 Y - 6.90 - 8.4 - 0.30 - - 0.22 -
Typical 0.75 7.00 3.75 8.5 5.25 0.35 - 0.68 0.25 -
Maximum - 7.10 - 8.6 - 0.40 1.20 - 0.27 0.08
Notes 1. Bump counts: 48 (8 row x 6 column). 2. Pitch: (x,y) = 0.75 mm x 0.75 mm (typ). 3. Units: millimeters. 4. All tolerance are 0.050 unless otherwise specified. 5. Typ: typical. 6. Y is coplanarity: 0.08 (max).
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Ordering codes
Speed (ns)
Ordering Code
AS6UA51216-TC AS6UA51216-BC AS6UA51216-TI AS6UA51216-BI
Package Type
44-pin TSOP II 48-ball fine pitch BGA 44-pin TSOP II 48-ball fine pitch BGA
Operating Range Commercial Industrial
55/70/100
Part numbering system
AS6UA SRAM IntelliwattTM prefix 51216 Device number B, T Package: T: TSOP II B: CSP BGA C, I Temperature range: C: Commercial: 0 C to 70 C I: Industrial: -40 C to 85 C
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Copyright (c)2000 Alliance Semiconductor Corporation (Alliance)'s three-point logo, our name, and IntelliwattTM are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this web site and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this web site. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as expressly agreed to in Alliance's Terms and Conditions of Sale (available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such lifesupporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.

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